1. The Field of the Invention
The present invention relates to the field of integrated circuits. More particularly, the present invention relates to an apparatus and method for debugging an electronic component or software executed by the electronic component to correct logical errors or programming errors, respectively.
2. Background of Art Related to the Invention
For many years, integrated circuit designers and software programmers have used an in-circuit emulator ("ICE.TM.") to debug software code or hardware, typically a central processing unit ("CPU") defined herein as an "intelligent" integrated circuit such as a microprocessor, micro-controller and the like. The ICE.TM. is a non-intrusive debugging tool that uses external hardware to emulate operations of the CPU embedded in a target system (i.e., a product prototype). As a result, certain results (output voltages, contents of storage elements, etc.) from these operations are traced (i.e., recorded) in memory of the ICE.TM..
The external hardware consists of a conventional testing probe which latches information from the CPU and directly uploads the information to an ICE.TM. base unit for storage in trace memory and later retrieval therefrom for debugging purposes. The conventional testing probe includes a number of programmable CMOS logic cell arrays ("LCAs") such as, for example, XC 2000 or 3000 series manufactured by Xilinx, Inc. of San Jose, Calif., which are electrically connected with the CPU mounted on the conventional testing probe. The CPU is then electrically connecting the target system as if it was embedded in the target system. The LCAs are arranged into a circuit for latching information from the CPU and transferring such information to the ICE.TM. base unit through a communication link. However, this construction affords many disadvantages.
One disadvantage associated with the conventional testing probe is that it merely transfers information between the CPU and the ICE.TM. base unit without being able to modifying the information in certain situations to reduce communication complexity between the LCAs and the ICE.TM. base unit as well as the LCAs themselves.
Another disadvantage associated with the conventional testing probe is that the LCAs typically can not support CPUs operating at high frequencies in the range of 65 mega-hertz ("MHz"). Thus, with advancements in CPU technology, these conventional testing probes will prohibit the ICE.TM. from debugging these CPUs and perhaps such software controlling the CPUs.
A further disadvantage is that LCAs within the conventional testing probe are incapable of performing a number of desired functions, including but not limited to filtering bus cycles for selectively tracing a particular type(s) of bus cycle(s), eliminating storage of unnecessary information in the ICE.TM. base unit (typically due to wait states and/or termination of the current bus cycle) and tracing snoop bus cycles to ascertain all activity on the CPU bus.
Yet another disadvantage associated with the conventional testing probe is that it is incapable of outputting information, particularly data and address, to the ICE.TM. base unit in a synchronous manner to increase performance efficiency by as much as fifty percent (50%).
Another disadvantage is that the conventional testing probe is incapable of generating address information required by the ICE.TM. base unit in the event that such address information is not provided by the CPU.
Therefore, it is contemplated that there exists a need for a circuit within the testing probe for enabling a CPU or software to be debugged at high operating frequencies (.gtoreq.65 MHz), reducing complexity of the ICE.TM. base unit and enabling many additional functions to be performed. Therefore, it is an object of the present invention to employ a circuit for assisting the ICE.TM. system for debugging purposes.
It is an object of the present invention to provide a circuit which reduces the complexity of the ICE.TM. system and thus, the complexity of the software controlling the ICE.TM. system.
It is another object of the present invention to provide a circuit for tracing the CPU bus during a DMA Operation by an external agent, provided the external agent abides by the specific protocol of the CPU.
Another object of the present invention is to allow software to begin at any location in the trace and start decoding bus cycles.
Yet another object of the present invention is to transmit packets of completed data to the ICE.TM. base unit for easy tracing of bus sequences, thereby avoiding errand data from being sent before completion of a desired bus cycle.
It is another object of the present invention to provide a circuit which increases the efficiency of the ICE.TM. base unit.
Another object of the present invention is to provide a circuit operating in conjunction with the ICE.TM. base unit to trace Snoop activities.